Bridging the Rails

Electronics Technical ArticlesSouth-East European INDUSTRIAL Мarket - issue 2/2007

Gaurang Kavaiya,
Microchip Technology Inc.

From the early days, the ‘mantra’ for the semiconductor industry has been “Smaller, Better, Faster and Cheaper”. The current Pocket PCs are more powerful than the first computer, which required a separate building. The way this goal has been achieved, so far, is to reduce the size of the individual transistor used to create the semiconductor device. This has an interesting side effect. As the transistor gets smaller, the operating voltage gets lower. The 5V power-supply rail used to be the most popular rail in embedded systems. However, most components in typical embedded systems are moving toward lower rails to take advantage of the latest trends in the industry. On the other hand, some components in the system take longer than others to transition. Therefore, in this transition phase it is possible that some components in the system may require different power-supply rails (i.e. a 5V device in a 3.3V system, and vice versa). This creates some design challenges for an embedded designer. One solution is to use level translators. However, the use of a level translator is not the most cost-efficient solution. This article discusses a few low-cost ideas to interface a 3.3V microcontroller (MCU) to a 5V peripheral.

When moving a 5V design to 3.3V, then the first thing to consider is a 3.3V version of the same device. In most cases, there will be an equivalent device supporting the 3.3V rail. Most of the time, 3.3V devices are available at either the same cost or cheaper. If an alternate device that runs at 3.3V is not available, then using two rails may be the answer. The main focus of this article is on designs that use two voltage rails.

When bringing two people from different worlds together, it is important to ensure that they can understand each other. The same is true when bringing the 5V world and the 3V world together. First comes an understanding of the voltage logic levels and input/output structure. For inputs, consider the voltage that is warranted to be detected as high input (VIH) and the voltage that is warranted to be detected as low input and (VIL). When interfacing a 3.3V system to a 5V device, the VIH tends to be a bigger problem than the VIL. However, it does not mean that the VIL spec can be ignored. The driving devices must output a voltage higher than the VIH(min) spec of the receiving device to ensure proper logic detection. Too high a voltage may also cause problems.

Almost all CMOS devices have some kind of Electro-Static Discharge (ESD) protection on all I/O pins. The most common way to implement this protection is to have a clamping diode to Vdd and Vss. Generally, this translates into a maximum input voltage spec of Vdd + 0.3V and a minimum voltage spec of Vss – 0.3V. If this spec is exceeded, then protection diodes may start conducting. If the input does not have a series resistor, then it may result in very high current through these diodes, potentially causing latch-up. Not a desirable condition. If the voltage is roughly high enough (i.e. 5V input in a 3.3V system), then the series resistor needs to be very high to reduce clamp current to a safe range. If the resistor is high enough, then the low-input capacitance due to pin capacitance and PCB layout may be significant and the RC time constant causes signal delay. Many manufacturers do not recommend the use of an ESD protection diode as a clamp diode, therefore, the use of a series resistor is not the best option to feed a 5V signal to a 3.3V device.

When considering the logic levels of a standard CMOS device, most tend to have VIH (min) of 0.7 Vdd or 0.8 Vdd. The VIL(max) tends to be in the region of 0.2 Vdd or 0.3 Vdd. For 5V logic, this translates into VIH of 3.5V or 4.0V and VIL(max) of 1.0V or 1.5V. Most CMOS devices output close to rail (0.1 or 0.2V drop) at a lower load. As the load current increases, VOH tends to be lower. In this scenario, the load current must be considered in order to determine the VOH.

Instead of an input series resistor, a better option is to use a resistor divider to bring the 5V signal in range for 3.3V input (see Figure 2). The resistor value should be selected in such a way that it accounts for all the tolerances. The following formulae assist in the calculation:

R2/(R1 + R2) * VOH (min) @ min of 5V (at maximum negative tolerance) > VIH(min)

R2/(R1 + R2) * VOH (max) @ max of 5V (at maximum positive tolerance) < VIH(max)

Resistor tolerance should also be a consideration in the above calculations.

Another, simpler solution is to use a 5V device with TTL inputs. The VIH(min) for a TTL device is 2.1V (for the Vdd of 5V). Most of the 3.3V devices can support a much higher VOH level at a high load rate. In this case, the solution is to replace the peripheral device with an equivalent device having TTL-compatible inputs.

A search should locate a suitable alternative with TTL inputs. Some examples are shown in Table 1.

If using a standard digital-logic family that must run at 5V, then equivalent devices with TTL inputs should be available. For example, the 74HCT family can be used to replace 74HC series devices. If a level translator is needed, then HCT or VHCT digital buffers can be used. In most situations, this TTL-input solution tends to be cheaper than the use of dedicated level translators.

The VOH level of the device operating at 3.3V is slightly below the VIH (0.7 Vdd = 3.5V) of the CMOS device operating at 5V. One simple solution is to use a diode to provide the required voltage shift.

The circuit shown in Figure 4 shifts the output by approximately 0.6V on the positive side. This shift of 0.6V to CMOS output brings it in range for 5V CMOS input. The same amount of shift is applied to the logic low signal. However, VIL (max) for the CMOS input tends to be around 1.5V, so the shifted signal will not violate the VIL spec. There are however several factors to be considered in this configuration. When the 3.3V device outputs a zero logic level, it increases the current draw. Examine the VOL spec of the 3.3V device for this current sink. Typically, the higher the sink current, the higher the VIL. Here, care should be taken to avoid violating the VIL spec. If the CMOS output VOL is higher, then increasing the pull-up resistor value can be considered. If the resistor value is too high, then the diode bias current will be low and the diode may not be able to switch fast.

Devices such as Microchip’s new PIC24 family of 16-bit microcontrollers offer one unique feature to simplify the 5V interface. They offer 5V (or 5.5V) tolerant inputs, even if the device runs at a Vdd of 3.3V or lower. They do not have a clamp diode to the Vdd and use a different type of ESD protection mechanism to support this capability. This is a very important feature for the 5V interface, as it allows a 5V output to be connected directly to a 3.3V device without a resistor divider. The example in Figure 3 shows that this feature allows for a seamless 5V interface.

Some microcontrollers further enhance this feature by providing the option to generate a 5V output with an external 5V pull-up resistor. The 3.3V device drives a 3.3V output, but it can tolerate a 5V input. The digitally-controlled open-drain output capability on these pins allows them to be pulled up to 5V without violating any specs. This feature supports a simple interface to 5V devices with CMOS inputs.

When using the pull-up resistor configuration shown in Figure 6, the capacitance of the connection between the two devices needs to be considered to determine the rise/fall rate (as does the maximum switching frequency) of the signal on this port pin, and the resistor value that is appropriate for the application.

Consider the following equation:

Rise/Falltime = t ln(PVdd/(PVdd - PVIH(min)))

Where t = RC time constant, R*C

PVdd = Vdd of the Peripheral voltage

PVIH(min) = The VIH (min) value of the peripheral

Using the following typical values:

Pull up resistor R = 1K

Resultant capacitance C due to pin and PCB capacitance = 10pF

PVdd = 5V

P VIH (min) = 0.7*Vdd = 3.5V

The resultant rise/ fall time >> 12nS

If the minimum acceptable pulse width for this rise/fall time is 50 nS, then it results in a maximum output frequency of 20 MHz. This is sufficient for most peripheral interactions.

This configuration has one side effect when the MCU drives the logic low; the extra current is burned through a pull-up resistor. The pull-up resistor offers design trade-offs for speed against current draw. It may be necessary to select a compromise value for the application that provides the required speed and current consumption for the application.

Some may say that this kind of configuration can not be used to drive a low-impedance load. So what are the options for driving a 5V relay? Fortunately, the above feature is also helpful for driving low-impedance loads like relays. Figure 7 shows the relevant circuit configuration. To drive the load, define the pin as an output and drive it low. The only limiting factor here is the current-sinking capability of the device. To turn off the load, define the pin as an input. This will turn the load off and will result in 5V at input. The pin is 5V-tolerant, so this is a valid operation. In other words, it is necessary to maintain logic low on output latch and toggle TRIS (input / output control register) to turn the load on / off.

This is an effective way to bridge the 5V and 3.3V rails. It is possible to devise similar low-cost, intelligent solutions to bridge two rails during the transition phase. It is also very likely that most devices will soon move to a lower rail, eliminating the need to bridge the rails. In the meantime, the methods described in this article should help designers to take advantage of the latest trends in the semiconductor industry and to lower system costs.




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